[all-commits] [llvm/llvm-project] f68477: GlobalISel: Include register class/bank in regbank...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f68477dda17e8238b75803170f89485c01bb541e
      https://github.com/llvm/llvm-project/commit/f68477dda17e8238b75803170f89485c01bb541e
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-01-29 (Sun, 29 Jan 2023)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

  Log Message:
  -----------
  GlobalISel: Include register class/bank in regbankselect debug printing