[all-commits] [llvm/llvm-project] 1d7961: [LLDB][RISCV] Add RVV registers enums

[Emmmer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1d7961fd1a36f0955423362932e1591e7d26ba9d
      https://github.com/llvm/llvm-project/commit/1d7961fd1a36f0955423362932e1591e7d26ba9d
  Author: Emmmer <yjhdandan at 163.com>
  Date:   2023-01-29 (Sun, 29 Jan 2023)

  Changed paths:
    M lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
    M lldb/source/Utility/RISCV_DWARF_Registers.h

  Log Message:
  -----------
  [LLDB][RISCV] Add RVV registers enums

RVV stands for "RISC-V V Extension", which adds 32 vector registers, and seven unprivileged CSRs (vstart, vxsat, vxrm, vcsr, vtype, vl, vlenb) to a base scalar RISC-V ISA.

The base vector extension is intended to provide general support for data-parallel execution within the 32-bit instruction encoding space, with later vector extensions supporting richer functionality for certain domains.

Reviewed By: DavidSpickett, kito-cheng

Differential Revision: https://reviews.llvm.org/D141898