[all-commits] [llvm/llvm-project] baf7f7: Recommit "Add optimizations for icmp eq/ne (mul(X, ...
goldsteinn via All-commits
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Fri Jan 27 18:39:17 PST 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: baf7f7e5752ceba898e1a434c4512de9d35863b0
https://github.com/llvm/llvm-project/commit/baf7f7e5752ceba898e1a434c4512de9d35863b0
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2023-01-27 (Fri, 27 Jan 2023)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp-binop.ll
M llvm/test/Transforms/InstCombine/pr38677.ll
Log Message:
-----------
Recommit "Add optimizations for icmp eq/ne (mul(X, Y), 0)" 2nd Try
First time caused build failure:
https://lab.llvm.org/buildbot/#/builders/183/builds/10447
but after investigating it seems to be unrelated. The same
test/build passed later with the original commit here:
https://lab.llvm.org/buildbot/#/builders/183/builds/10448
1. Add checks if X and/or Y are odd. The Odd values are unnecessary to
the icmp: isZero(Odd * N) == isZero(N)
2. If neither X nor Y is known odd, then if X * Y cannot overflow AND
if X and/or Y is non-zero, the non-zero values are unnecessary to the
icmp.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D140850
Commit: c17ccced4b0ba2152a05e7a137c392dbd14181ad
https://github.com/llvm/llvm-project/commit/c17ccced4b0ba2152a05e7a137c392dbd14181ad
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2023-01-27 (Fri, 27 Jan 2023)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
M llvm/test/Transforms/InstCombine/shift-logic.ll
Log Message:
-----------
Recommit "Reorder (shl (add/sub (shl x, C0), y), C1) -> (add/sub (shl x, C0 + C1), (shl y, C1))" 2nd Try
First time caused build failure:
https://lab.llvm.org/buildbot/#/builders/183/builds/10447
but after investigating it seems to be unrelated. The same
test/build passed later with the original commit here:
https://lab.llvm.org/buildbot/#/builders/183/builds/10448
This is just expanding the existing pattern that exists for AND/XOR/OR
and gets a bit more parallelism in from the instruction sequence.
Alive2:
Add - https://alive2.llvm.org/ce/z/dSmPkV
Sub1 - https://alive2.llvm.org/ce/z/6rpi5V
Sub2 - https://alive2.llvm.org/ce/z/UfYeUd
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D141875
Compare: https://github.com/llvm/llvm-project/compare/09b7692c6259...c17ccced4b0b
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