[all-commits] [llvm/llvm-project] 44977a: Add tests for binops with conditions/assume constr...

[goldsteinn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 44977a155f24be3cdbcd2a57acbfd6da2529abde
      https://github.com/llvm/llvm-project/commit/44977a155f24be3cdbcd2a57acbfd6da2529abde
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-01-27 (Fri, 27 Jan 2023)

  Changed paths:
    A llvm/test/Transforms/InstCombine/icmp-binop.ll

  Log Message:
  -----------
  Add tests for binops with conditions/assume constraints

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D140849


  Commit: aa250ceb3ff15d55bb506b4bc8196f143133d8b5
      https://github.com/llvm/llvm-project/commit/aa250ceb3ff15d55bb506b4bc8196f143133d8b5
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-01-27 (Fri, 27 Jan 2023)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
    M llvm/test/Transforms/InstCombine/icmp-binop.ll
    M llvm/test/Transforms/InstCombine/pr38677.ll

  Log Message:
  -----------
  Add optimizations for icmp eq/ne (mul(X, Y), 0)

1. Add checks if X and/or Y are odd. The Odd values are unnecessary to
   the icmp: isZero(Odd * N) == isZero(N)

2. If neither X nor Y is known odd, then if X * Y cannot overflow AND
   if X and/or Y is non-zero, the non-zero values are unnecessary to the
   icmp.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D140850


  Commit: 8c884655862ed2e4ca0f00de349387db77294c8b
      https://github.com/llvm/llvm-project/commit/8c884655862ed2e4ca0f00de349387db77294c8b
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-01-27 (Fri, 27 Jan 2023)

  Changed paths:
    M llvm/test/Transforms/InstCombine/shift-logic.ll

  Log Message:
  -----------
  Add tests for reoredering (shift (add (shift x, C0), y), C1); NFC

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D141874


  Commit: edd80befeeb92000800ded2a6f3dcdfd672d95ea
      https://github.com/llvm/llvm-project/commit/edd80befeeb92000800ded2a6f3dcdfd672d95ea
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-01-27 (Fri, 27 Jan 2023)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
    M llvm/test/Transforms/InstCombine/shift-logic.ll

  Log Message:
  -----------
  Reorder (shl (add/sub (shl x, C0), y), C1) -> (add/sub (shl x, C0 + C1), (shl y, C1))

This is just expanding the existing pattern that exists for AND/XOR/OR
and gets a bit more parallelism in from the instruction sequence.

Alive2:
Add  - https://alive2.llvm.org/ce/z/dSmPkV
Sub1 - https://alive2.llvm.org/ce/z/6rpi5V
Sub2 - https://alive2.llvm.org/ce/z/UfYeUd

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D141875


Compare: https://github.com/llvm/llvm-project/compare/03d136cf5f3f...edd80befeeb9