[all-commits] [llvm/llvm-project] 939408: [SVE][InstrFormats] Explcitly set hasSideEffects f...

[paulwalker-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9394088ca02693b3b7d98c2996f42ce653255e7d
      https://github.com/llvm/llvm-project/commit/9394088ca02693b3b7d98c2996f42ce653255e7d
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2023-01-25 (Wed, 25 Jan 2023)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
    M llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s

  Log Message:
  -----------
  [SVE][InstrFormats] Explcitly set hasSideEffects for all SVE instructions.

The instruction property hasSideEffects relies on the presence of
tablegen isel patterns when constructing its value, unless
specifically overriden. Since adding SVE scheduling information
we've noticed this property flip-flop as isel patterns have been
updated. To make things consistent (and correct) this patch
explicitly sets the property for all SVE instructions.

This has resulted in the following notable changes:
* Normal load and store instructions no longer report having side
  effects.
* All prefetch instructions correctly report having side effects.
* FFR related instructions continue to report having side effects.
  This is likely overkill but I've chosen to remain cautious here.
* Most all integer instructions no longer report having side effects.
* Most all floating point instructions no longer report having side
  effects, but do now report their potential for raising FP
  exceptions. I do not know how to test the latter so I've again
  took a caution route of taging all floating point instructions
  except for DUPs.
* The conflict detection intrinsics now report they don't touch
  memory.

NOTE: SVE isel makes significant use of psuedo instructions but
this patch makes no effort to update them.

NOTE: We'll need a similar patch for SME but without a scheduling
model it'll be harder to verify the results.

Differential Revision: https://reviews.llvm.org/D142122