[all-commits] [llvm/llvm-project] 778cf5: IR: Add atomicrmw uinc_wrap and udec_wrap

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 778cf5431cafc243f81dd5c8cbd27701ff7f9120
      https://github.com/llvm/llvm-project/commit/778cf5431cafc243f81dd5c8cbd27701ff7f9120
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-01-24 (Tue, 24 Jan 2023)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/include/llvm/AsmParser/LLToken.h
    M llvm/include/llvm/Bitcode/LLVMBitCodes.h
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
    M llvm/include/llvm/IR/Instructions.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/GenericOpcodes.td
    M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/include/llvm/Transforms/Utils/LowerAtomic.h
    M llvm/lib/AsmParser/LLLexer.cpp
    M llvm/lib/AsmParser/LLParser.cpp
    M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
    M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
    M llvm/lib/CodeGen/AtomicExpandPass.cpp
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
    M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
    M llvm/lib/IR/Instructions.cpp
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Transforms/Utils/LowerAtomic.cpp
    M llvm/test/Assembler/atomic.ll
    M llvm/test/Bitcode/compatibility.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    A llvm/test/CodeGen/AArch64/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
    A llvm/test/CodeGen/ARM/atomicrmw-uinc-udec-wrap.ll
    A llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll
    A llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll
    A llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll
    A llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    A llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
    A llvm/test/CodeGen/VE/Scalar/atomicrmw-uinc-udec-wrap.ll
    A llvm/test/CodeGen/WebAssembly/atomicrmw-uinc-udec-wrap.ll
    A llvm/test/CodeGen/X86/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
    M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll

  Log Message:
  -----------
  IR: Add atomicrmw uinc_wrap and udec_wrap

These are essentially add/sub 1 with a clamping value.

AMDGPU has instructions for these. CUDA/HIP expose these as
atomicInc/atomicDec. Currently we use target intrinsics for these,
but those do no carry the ordering and syncscope. Add these to
atomicrmw so we can carry these and benefit from the regular
legalization processes.