[all-commits] [llvm/llvm-project] fb0af8: [AArch64] Add the Ampere1A core

[Philipp Tomsich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fb0af89193a9ea0f92eaffb454341987f897f0c7
      https://github.com/llvm/llvm-project/commit/fb0af89193a9ea0f92eaffb454341987f897f0c7
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2023-01-24 (Tue, 24 Jan 2023)

  Changed paths:
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/include/llvm/TargetParser/AArch64TargetParser.h
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
    M llvm/lib/Target/AArch64/AArch64Subtarget.h
    M llvm/lib/TargetParser/Host.cpp
    M llvm/test/CodeGen/AArch64/cpus.ll
    M llvm/test/CodeGen/AArch64/neon-dot-product.ll
    M llvm/test/CodeGen/AArch64/remat.ll
    M llvm/test/MC/AArch64/armv8.2a-dotprod.s
    M llvm/test/MC/AArch64/armv8.3a-rcpc.s
    M llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
    M llvm/unittests/TargetParser/Host.cpp
    M llvm/unittests/TargetParser/TargetParserTest.cpp

  Log Message:
  -----------
  [AArch64] Add the Ampere1A core

The Ampere1A core improves on the Ampere1 with key differences being:
 * memory tagging is supported
 * SM3/SM4 are supported
 * adds a new fusion pair for (A+B+1 and A-B-1)
   (added in a later commit)

Depends on D142395

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D142396