[all-commits] [llvm/llvm-project] f5a644: [RISCV] Combine FP_TO_INT to vfwcvt/fvncvt

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f5a644719657c25bdb298c17374578d2e9202197
      https://github.com/llvm/llvm-project/commit/f5a644719657c25bdb298c17374578d2e9202197
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-01-24 (Tue, 24 Jan 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll

  Log Message:
  -----------
  [RISCV] Combine FP_TO_INT to vfwcvt/fvncvt

Adds new pseudo instructions to make sure that the fcvt instructions
have all rounding mode (RM) and unsigned (XU) variants across
single-width, widening and narrowing conversions.
And likewise, extends the VL patterns to accompany them. We don't add
new VL nodes for the widening/narrowing conversions though, instead we
just add specific patterns for vfcvts on those wider/narrower types.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D142102