[all-commits] [llvm/llvm-project] ecbf5d: [6/15][Clang][RISCV][NFC] Instructions with a mask...

[Yueh-Ting (eop) Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ecbf5db88d285f72fbd0126be9c20f790d603b23
      https://github.com/llvm/llvm-project/commit/ecbf5db88d285f72fbd0126be9c20f790d603b23
  Author: eopXD <yueh.ting.chen at gmail.com>
  Date:   2023-01-24 (Tue, 24 Jan 2023)

  Changed paths:
    M clang/include/clang/Support/RISCVVIntrinsicUtils.h
    M clang/lib/Support/RISCVVIntrinsicUtils.cpp

  Log Message:
  -----------
  [6/15][Clang][RISCV][NFC] Instructions with a mask destination register is always tail agnostic

The logic under `computeBuiltinTypes` is an amendment to setting Policy as
`Omit`. The tail policy should be set to agnostic for those intrinsics that
has `HasTailPolicy = false`, which are the intrinsics with a mask destination
register.

This is the 6th commit of a patch-set that aims to change the default policy
for RVV intrinsics from TAMU to TAMA.

Please refer to the cover letter in the 1st commit (D141573) for an
overview.

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://reviews.llvm.org/D141756