[all-commits] [llvm/llvm-project] a6a4fe: [NFC][WoA] Precommit test for aarch64 atomics

[Usman Nadeem via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a6a4fe203f3cd8cdae2a7b23b1993718021cb43a
      https://github.com/llvm/llvm-project/commit/a6a4fe203f3cd8cdae2a7b23b1993718021cb43a
  Author: Nadeem, Usman <mnadeem at quicinc.com>
  Date:   2023-01-23 (Mon, 23 Jan 2023)

  Changed paths:
    A llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll

  Log Message:
  -----------
  [NFC][WoA] Precommit test for aarch64 atomics

This copies the atomic-ops file.
Committed without review.

Differential Revision: https://reviews.llvm.org/D141964

Change-Id: I7d7b05339d9ca23f88848c56f73a3e4d3e1abeba


  Commit: c9821abfc023fba684c8ef8589c49cba8083f579
      https://github.com/llvm/llvm-project/commit/c9821abfc023fba684c8ef8589c49cba8083f579
  Author: Nadeem, Usman <mnadeem at quicinc.com>
  Date:   2023-01-23 (Mon, 23 Jan 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/AtomicExpandPass.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll

  Log Message:
  -----------
  [WoA] Use fences for sequentially consistent stores/writes

LLVM currently uses LDAR/STLR and variants for acquire/release
as well as seq_cst operations. This is fine as long as all code uses
this convention.

Normally LDAR/STLR act as one way barriers but when used in
combination they provide a sequentially consistent model. i.e.
when an LDAR appears after an STLR in program order the STLR
acts as a two way fence and the store will be observed before
the load.

The problem is that normal loads (unlike ldar), when they appear
after the STLR can be observed before STLR (if my understanding
is correct). Possibly providing weaker than expected guarantees if
they are used for ordered atomic operations.

Unfortunately in Microsoft Visual Studio STL seq_cst ld/st are
implemented using normal load/stores and explicit fences:
dmb ish + str + dmb ish
ldr + dmb ish

This patch uses fences for MSVC target whenever we write to the
memory in a sequentially consistent way so that we don't rely on
the assumptions that just using LDAR/STLR will give us sequentially
consistent ordering.

Differential Revision: https://reviews.llvm.org/D141748

Change-Id: I48f3500ff8ec89677c9f089ce58181bd139bc68a


Compare: https://github.com/llvm/llvm-project/compare/eba322e9d724...c9821abfc023