[all-commits] [llvm/llvm-project] d1c0fe: [AMDGPU] Tune scheduler on GFX10 and GFX11 for reg...

[Stanislav Mekhanoshin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d1c0febeab41bcdda30c29d8e99a5fc83ffb24fc
      https://github.com/llvm/llvm-project/commit/d1c0febeab41bcdda30c29d8e99a5fc83ffb24fc
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2023-01-23 (Mon, 23 Jan 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
    A llvm/test/CodeGen/AMDGPU/schedule-avoid-spills.ll

  Log Message:
  -----------
  [AMDGPU] Tune scheduler on GFX10 and GFX11 for regions with spilling

Unlike older ASICs GFX10+ have a lot of VGPRs. Therefore, it is possible
to achieve high occupancy even with all or almost all addressable VGPRs
used. Our scheduler was never tuned for this scenario. The VGPR Critical
Limit threshold always comes very high, even if maximum occupancy is
targeted. For example on gfx1100 it is set to 192 registers even with
the requested occupancy 16. As a result scheduler starts prioritizing
register pressure reduction very late and we easily end up spilling.

This patch makes VGPR critical limit similar to what we would have on
pre-gfx10 targets with much more limited VGPR budget while still trying
to maintain occupancy as it does now.

Pre-gfx10 ASICs shall not be affected as the limit shall be the same
as before, and on gfx10+ it shall only affect regions where we have
to spill.

Fixes: SWDEV-377300

Differential Revision: https://reviews.llvm.org/D141876