[all-commits] [llvm/llvm-project] 5f6a97: [AArch64][SME2] Add multi-vector convert to/from f...

[CarolineConcatto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5f6a97115759625fb3cbf61457cb8b4c6c3f8399
      https://github.com/llvm/llvm-project/commit/5f6a97115759625fb3cbf61457cb8b4c6c3f8399
  Author: Caroline Concatto <caroline.concatto at arm.com>
  Date:   2023-01-23 (Mon, 23 Jan 2023)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sme2-intrinsics-cvt.ll

  Log Message:
  -----------
  [AArch64][SME2] Add multi-vector convert to/from floating-point intrinsic

Add the following intrinsic:

  FCVT
  BFCVT
  FCVTZS
  FCVTZU
  SCVTF
  UCVTF

This patch also adds SelectCVTIntrinsic to handle the cases when the
intrinsic returns multiple (two or four) outputs

NOTE: These intrinsics are still in development and are subject to future changes.

Reviewed By: kmclaughlin

Differential Revision: https://reviews.llvm.org/D142032