[all-commits] [llvm/llvm-project] 88eae6: [DAGCombine]Expand usage of CreateBuildVecShuffle ...

[XinWang10 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 88eae6ef9fb527bfd979c1672e2ed07f77136fbd
      https://github.com/llvm/llvm-project/commit/88eae6ef9fb527bfd979c1672e2ed07f77136fbd
  Author: Wang, Xin10 <xin10.wang at intel.com>
  Date:   2023-01-23 (Mon, 23 Jan 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/avg.ll
    M llvm/test/CodeGen/X86/pr29112.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll

  Log Message:
  -----------
  [DAGCombine]Expand usage of CreateBuildVecShuffle to make full use of vector ops

Now, when llc encounters the case that contains a lot of
extract_vector_elt and a BUILD_VECTOR, it will replace these to
vector_shuffle to decrease the size of code, the actions are done in
createBuildVecShuffle in DAGCombiner.cpp, but now the code cannot handle
the case that the size of source vector reg is more than twice the dest
size.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D139685