[all-commits] [llvm/llvm-project] 42afa1: [AArch64] Simplify isSeveralBitsExtractOpFromShr (...

[kazutakahirata via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 42afa168cdcca1d3307b1fe94534fffb269c1265
      https://github.com/llvm/llvm-project/commit/42afa168cdcca1d3307b1fe94534fffb269c1265
  Author: Kazu Hirata <kazu at google.com>
  Date:   2023-01-21 (Sat, 21 Jan 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

  Log Message:
  -----------
  [AArch64] Simplify isSeveralBitsExtractOpFromShr (NFC)

This patch simplifies isSeveralBitsExtractOpFromShr.

The following statements are equivalent:

  unsigned BitWide = 64 - countLeadingOnes(~(AndMask >> SrlImm));
  unsigned BitWide = 64 - countLeadingZeros(AndMask >> SrlImm);

Now, consider:

  if (BitWide && isMask_64(AndMask >> SrlImm)) {

When isMask_64 returns true, AndMask >> SrlImm and BitWide must be
nonzero.  Since BitWide does not contribute to narrowing the
condition, we can simplify the condition as:

  if (isMask_64(AndMask >> SrlImm)) {

We can negate the condition for an early exit as recommended by the
LLVM Coding Standards.

Now, all of the following are equivalent if AndMask >> SrlImm is
nonzero:

  MSB = BitWide + SrlImm - 1
  MSB = (64 - countLeadingZero(AndMask >> SrlImm)) + SrlImm - 1
  MSB = (63 - countLeadingZero(AndMask >> SrlImm)) + SrlImm
  MSB = 63 - countLeadingZero(AndMask)
  MSB = 63 ^ countLeadingZero(AndMask)
  MSB = findLastSet(AndMask, ZB_Undefined)