[all-commits] [llvm/llvm-project] b3154d: [ARM][AArch64] Switch to generic MEMBARRIER node

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b3154d08e948c37872bf053f90b6728e7d39039b
      https://github.com/llvm/llvm-project/commit/b3154d08e948c37872bf053f90b6728e7d39039b
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-01-20 (Fri, 20 Jan 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMScheduleA57.td
    M llvm/test/CodeGen/AArch64/fence-singlethread.ll
    M llvm/test/CodeGen/ARM/fence-singlethread.ll

  Log Message:
  -----------
  [ARM][AArch64] Switch to generic MEMBARRIER node

This change switches both targets from using target specific CompilerBarrier nodes to the recently introduced generic MEMBARRIER instruction.

A couple things to call out.

First, this changes the assembly comment printed. I'm not sure this matters, but if it does, we can simply drop this patch. This is a minor clean up at best.

Second, the ordering operand on the target instruction appears to be unused. We could easily add ordering to the generic instruction, but since we don't seem to have a motivating case in tree, I simply dropped the ordering when selecting to the generic instruction.

Differential Revision: https://reviews.llvm.org/D141513