[all-commits] [llvm/llvm-project] d0942d: [AArch64][SVE] Add more intrinsics in 'isZeroingIn...

[Allen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d0942df43e5eb02bdcc44d499d62924214feef63
      https://github.com/llvm/llvm-project/commit/d0942df43e5eb02bdcc44d499d62924214feef63
  Author: chendewen <chendewen3 at huawei.com>
  Date:   2023-01-18 (Wed, 18 Jan 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/sve2-intrinsics-reinterpret.ll

  Log Message:
  -----------
  [AArch64][SVE] Add more intrinsics in 'isZeroingInactiveLanes'.

The REINTERPRET_CAST operation generates redundant and and ptrue instructions.
For some instructions, this is redundant, because its inactive lanes are zeroed by construction.
For example. Codegen before:
```
facgt p2.d, p0/z, z4.d, z1.d
ptrue p1.d
and p1.b, p2/z, p2.b, p1.b
```
After:
```
facgt p1.d, p0/z, z4.d, z1.d
```
ref: https://reviews.llvm.org/D129851

Reviewed By:sdesmalen,paulwalker-arm

Differential Revision:https://reviews.llvm.org/D141469