[all-commits] [llvm/llvm-project] a971ce: [RISCV] Eliminate the need to pass both RISCVSubta...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a971ce70aa0431aacdbdc39a0913d9c83cadfc3e
      https://github.com/llvm/llvm-project/commit/a971ce70aa0431aacdbdc39a0913d9c83cadfc3e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-01-17 (Tue, 17 Jan 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [RISCV] Eliminate the need to pass both RISCVSubtarget and MCSubtargetInfo to isCompressibleInst.

RISCVSubtarget should be a superclass of MCSubtargetInfo so should
have all the same information. Now we pass RISCVSubtarget by
reference and name it STI.

Confusingly, we seem to have been using an MCSubtargetInfo from
the TargetMachine rather than the one associated with the function
we are operating. I'm going to assume that was a mistake and not
intentional.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D141966