[all-commits] [llvm/llvm-project] 29f5e9: [RISCV] Use zeroext instead of signext in mask red...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 29f5e9e6f097e994d78f8bd5e64180a0267ca1eb
      https://github.com/llvm/llvm-project/commit/29f5e9e6f097e994d78f8bd5e64180a0267ca1eb
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-01-17 (Tue, 17 Jan 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll

  Log Message:
  -----------
  [RISCV] Use zeroext instead of signext in mask reduction tests. NFC

This is more consistent with ABI and how bools on RISC-V are
represented.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D141963