[all-commits] [llvm/llvm-project] 226cee: [RISCV] Use Zvl*b as a lower bound for VScaleRange.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 226ceebfa232492d0c4613cd6c9f8e72b970fe08
      https://github.com/llvm/llvm-project/commit/226ceebfa232492d0c4613cd6c9f8e72b970fe08
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-01-17 (Tue, 17 Jan 2023)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/test/CodeGen/riscv-vector-bits-vscale-range.c

  Log Message:
  -----------
  [RISCV] Use Zvl*b as a lower bound for VScaleRange.

The backend has a fatal error in RISCVSubtarget::getMinRVVVectorSizeInBits
if RVVVectorBitsMin is less than the Zvl length from -march. Now
RVVVectorBitsMin is connected to VScaleRange in the backend, we
can trip this fatal error.

This patch adds the Zvl*b length as a lower bound to protect this.
The test is updated to test vscale-min with Zvl64b instead of V.

I'd like to do a proper diagnostic for this, but I don't think we
can do that from this function. Since -mvscale-min is an internal cc1
option, I'm not sure it's a big deal.

I'm planning to add a driver option -msve-vector-bits. I will
probably implement a diagnostic for that.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D141459