[all-commits] [llvm/llvm-project] 1f2c37: [AArch64][SVE] Implement isVScaleKnownToBeAPowerOfTwo

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1f2c37afbe69d048bc518363454ae073f588066e
      https://github.com/llvm/llvm-project/commit/1f2c37afbe69d048bc518363454ae073f588066e
  Author: David Green <david.green at arm.com>
  Date:   2023-01-17 (Tue, 17 Jan 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/test/CodeGen/AArch64/vscale-power-of-two.ll

  Log Message:
  -----------
  [AArch64][SVE] Implement isVScaleKnownToBeAPowerOfTwo

According to https://developer.arm.com/documentation/102105/ia-00/?lang=en

> Arm is making a retrospective change to the SVE architecture to remove
> the capability of selecting a non-power-of-two vector length in
> non-Streaming SVE as well as in Streaming SVE mode. Specific updates as
> a result of this change will be communicated in due course.

This patch implements the isVScaleKnownToBeAPowerOfTwo method to teach
DAG Combines that VScale will be known to be a power of 2, which helps
reduce or simplify some expressions (notably the udiv in vector trip
count expressions).

Differential Revision: https://reviews.llvm.org/D141486