[all-commits] [llvm/llvm-project] 4954c3: [RISCV] Generate march string from target features

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4954c3c7b690c3cb484f6d18d3f3927aa65e21f4
      https://github.com/llvm/llvm-project/commit/4954c3c7b690c3cb484f6d18d3f3927aa65e21f4
  Author: wangpc <pc.wang at linux.alibaba.com>
  Date:   2023-01-16 (Mon, 16 Jan 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

  Log Message:
  -----------
  [RISCV] Generate march string from target features

As what has been mentioned in D137517, this patch is to simplify
processors definitions in RISCV.td. We don't have to specify march
string since we can generate it from target features.

Reviewed By: fpetrogalli, kito-cheng

Differential Revision: https://reviews.llvm.org/D141479