[all-commits] [llvm/llvm-project] 79858d: [CodeGen][Target] Remove uses of Register::isPhysi...
Craig Topper via All-commits
all-commits at lists.llvm.org
Fri Jan 13 23:13:16 PST 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 79858d1908b53560941b7d8f4d98e5ac781c674b
https://github.com/llvm/llvm-project/commit/79858d1908b53560941b7d8f4d98e5ac781c674b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
M llvm/include/llvm/CodeGen/LiveRegUnits.h
M llvm/include/llvm/CodeGen/MachineInstrBuilder.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/Register.h
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
M llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
M llvm/lib/Target/ARM/A15SDOptimizer.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMCallLowering.cpp
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstructionSelector.cpp
M llvm/lib/Target/ARM/ARMScheduleA9.td
M llvm/lib/Target/ARM/MLxExpansionPass.cpp
M llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
M llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
M llvm/lib/Target/BPF/BPFMIPeephole.cpp
M llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
M llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/MipsInstructionSelector.cpp
M llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
M llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXPeephole.cpp
M llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
M llvm/lib/Target/PowerPC/PPCMacroFusion.cpp
M llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
M llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
M llvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
M llvm/lib/Target/X86/X86DomainReassignment.cpp
M llvm/lib/Target/X86/X86ExpandPseudo.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86OptimizeLEAs.cpp
M llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
Log Message:
-----------
[CodeGen][Target] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC
Use isPhysical/isVirtual methods.
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