[all-commits] [llvm/llvm-project] a6f113: [AArch64][SVE] Avoid AND operation if both side ar...

[Dinar Temirbulatov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a6f1134b095a6ac3694b0dc40c153dc3ce35e113
      https://github.com/llvm/llvm-project/commit/a6f1134b095a6ac3694b0dc40c153dc3ce35e113
  Author: Dinar Temirbulatov <dinar.temirbulatov at arm.com>
  Date:   2023-01-11 (Wed, 11 Jan 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
    A llvm/test/CodeGen/AArch64/sve-splat-one-and-ptrue.ll

  Log Message:
  -----------
  [AArch64][SVE] Avoid AND operation if both side are splat of i1 or PTRUE

If both sides of AND operations are i1 splat_vectors or PTRUE node then we can
produce just i1 splat_vector as the result.

Differential Revision: https://reviews.llvm.org/D141043