[all-commits] [llvm/llvm-project] 47cc1b: [RISCV] Add test cases for PR59345. NFC

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 47cc1b9d29eab4ab355c96ed1c6a39226a99e12d
      https://github.com/llvm/llvm-project/commit/47cc1b9d29eab4ab355c96ed1c6a39226a99e12d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-01-09 (Mon, 09 Jan 2023)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll

  Log Message:
  -----------
  [RISCV] Add test cases for PR59345. NFC

These tests show failure to form vwadd(u).wv instructions.

One of the operands of the add is already wide and has an
additional user. We are unnecessary enforcing that operand to
have a single use.


  Commit: 3f191770fa7682347f150dd2c4c98cad4ae211f2
      https://github.com/llvm/llvm-project/commit/3f191770fa7682347f150dd2c4c98cad4ae211f2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-01-09 (Mon, 09 Jan 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll

  Log Message:
  -----------
  [RISCV] Update combineBinOp_VLToVWBinOp_VL to check the number users after we know what combine we're going to do.

If we're forming vwadd(u).wv we don't care if the already wide
source operand has additional users. It's not affected by the
transform.

Fixes #59345


  Commit: 64fae4d3b7837007b1cc836fbc9b6b7549f3a5f1
      https://github.com/llvm/llvm-project/commit/64fae4d3b7837007b1cc836fbc9b6b7549f3a5f1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-01-09 (Mon, 09 Jan 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns to form tail undisturbed vwadd(u).wv from vwadd(u)_vl+vp_merge.

We use a special TIED instructions for vwadd(u).wv to avoid an
earlyclobber constraint preventing the first source and the destination
from being the same register.

This prevents our normal post process for forming TU instructions.
Add manual isel pattern instead. This matches what we do for FMA
for example.


Compare: https://github.com/llvm/llvm-project/compare/1b9ba5856add...64fae4d3b783