[all-commits] [llvm/llvm-project] 596c55: [AMDGPU] More selectively attach implicit operands...

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 596c5581556cbd4103d982066fb76e745fb8480e
      https://github.com/llvm/llvm-project/commit/596c5581556cbd4103d982066fb76e745fb8480e
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2023-01-09 (Mon, 09 Jan 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
    A llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
    M llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir

  Log Message:
  -----------
  [AMDGPU] More selectively attach implicit operands to agpr spills

Implicit def operands are needed when we spill partially undef super registers by each individual subregister. The implicit-def operands will allow us to lower spills without the verifier complaining. Currently, we are overzeously attaching implicit operands, when we really only need them on the first sub reg spill op. By more selectively attached the implicit ops, we will free up some unneeded dependencies for the post-ra scheduler.

Moreover, this enables a previously incorrect optimization / resolves a correctness issue in indirectCopyToAGPR. When lowering AGPR copies on GFX908, we can improve CodeGen by reusing accvgpr_writes. However, we could not reliably determine which agprs accvgpr_writes actually define due to implicit-defs.

Differential Revision: https://reviews.llvm.org/D141101