[all-commits] [llvm/llvm-project] 1aa986: [RISCV] Add more XVentanaCondOps patterns.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1aa9862df3634d1d526e5bfd0431408a24ac435a
      https://github.com/llvm/llvm-project/commit/1aa9862df3634d1d526e5bfd0431408a24ac435a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-01-06 (Fri, 06 Jan 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
    M llvm/test/CodeGen/RISCV/select.ll
    M llvm/test/CodeGen/RISCV/xventanacondops.ll

  Log Message:
  -----------
  [RISCV] Add more XVentanaCondOps patterns.

Add patterns with seteq/setne conditions.

We don't have instructions for seteq/setne except for comparing
with zero and need to emit an ADDI or XOR before a seqz/snez to
compare other values.

The select ISD node takes a 0/1 value for the condition, but the
VT_MASKC(N) instructions check all XLen bits for zero or non-zero.
We can use this to avoid the seqz/snez in many cases.

This is pretty ridiculous number of patterns. I wonder if we could
use some ComplexPatterns to merge them, but I'd like to do that as
a follow up and focus on correctness of the result in this patch.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D140421