[all-commits] [llvm/llvm-project] e5a71a: [RISCV] Add support for the vscale_range attribute.
Craig Topper via All-commits
all-commits at lists.llvm.org
Fri Jan 6 08:21:12 PST 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: e5a71a41d8e043a502d88b42a69f5731faa17849
https://github.com/llvm/llvm-project/commit/e5a71a41d8e043a502d88b42a69f5731faa17849
Author: Craig Topper <craig.topper at sifive.com>
Date: 2023-01-06 (Fri, 06 Jan 2023)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll
M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
Log Message:
-----------
[RISCV] Add support for the vscale_range attribute.
This is based on @frasercrmck's D107290. At least some of the clang
portion of D107290 has already been committed.
This uses vscale_range for min/max vector width unless the command
line overrides are used.
As a follow up, I plan to add a max or exact VLEN option to clang
to control the vscale_range. This will eliminate many of the reasons
for users to use the overrides through the -mllvm interface.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D139873
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