[all-commits] [llvm/llvm-project] 239a17: [RISCV] Prevent constant hoisting for or/and/xor t...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 239a174d92dd2bd99ecb1308dc8937040895b04d
      https://github.com/llvm/llvm-project/commit/239a174d92dd2bd99ecb1308dc8937040895b04d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-01-05 (Thu, 05 Jan 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll

  Log Message:
  -----------
  [RISCV] Prevent constant hoisting for or/and/xor that can use bseti/bclri/binvi.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D140928