[all-commits] [llvm/llvm-project] 11e92b: [SelectionDAG] Improve codegen for udiv by constan...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 11e92bd61fd640bb1c833b0e185979d80204eb9e
      https://github.com/llvm/llvm-project/commit/11e92bd61fd640bb1c833b0e185979d80204eb9e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-01-05 (Thu, 05 Jan 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
    M llvm/test/CodeGen/X86/combine-udiv.ll

  Log Message:
  -----------
  [SelectionDAG] Improve codegen for udiv by constant if any divisors are 1.

If the divisor is 1, the magic algorithm does not return a correct
result and we end up using a select to pick the numerator for those
elements at the end.

Therefore we can use undef for that element of the earlier operations
when the divisor is 1. We sometimes get this through SimplifyDemandedVectorElts,
but not always. Definitely seems like we don't if the NPQ fixup is used.

Unfortunately, DAGCombiner is unable to fold srl X, <0, undef> to X so
I had to add flags to avoid emitting the srl unless one of the shift
amounts is non-zero.

Reviewed By: lebedev.ri

Differential Revision: https://reviews.llvm.org/D141022