[all-commits] [llvm/llvm-project] 60442f: [CodeGen] Convert some tests to opaque pointers (NFC)

Nikita Popov via All-commits all-commits at lists.llvm.org
Thu Jan 5 04:23:21 PST 2023 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 60442f0d442723a487528bdd8b48b24657a025e8
      https://github.com/llvm/llvm-project/commit/60442f0d442723a487528bdd8b48b24657a025e8
  Author: Nikita Popov <npopov at redhat.com>
  Date:   2023-01-05 (Thu, 05 Jan 2023)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
    M llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll
    M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
    M llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
    M llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
    M llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
    M llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
    M llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
    M llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir
    M llvm/test/CodeGen/AMDGPU/load-store-opt-dlc.mir
    M llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir
    M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
    M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.mir
    M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
    M llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
    M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
    M llvm/test/CodeGen/AMDGPU/sched-barrier-post-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
    M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir
    M llvm/test/CodeGen/AMDGPU/schedule-ilp.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
    M llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir
    M llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt.mir
    M llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir
    M llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
    M llvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir
    M llvm/test/CodeGen/ARM/cmse-clear-float-bigend.mir
    M llvm/test/CodeGen/ARM/codesize-ifcvt.mir
    M llvm/test/CodeGen/ARM/const-load-align-thumb.mir
    M llvm/test/CodeGen/ARM/dbg-range-extension.mir
    M llvm/test/CodeGen/ARM/fp16-litpool-arm.mir
    M llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir
    M llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir
    M llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
    M llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
    M llvm/test/CodeGen/ARM/machine-sink-multidef.mir
    M llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir
    M llvm/test/CodeGen/ARM/noreturn-csr-skip.mir
    M llvm/test/CodeGen/ARM/pei-swiftself.mir
    M llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir
    M llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir
    M llvm/test/CodeGen/ARM/single-issue-r52.mir
    M llvm/test/CodeGen/ARM/stack_frame_offset.mir
    M llvm/test/CodeGen/ARM/store-prepostinc.mir
    M llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir
    M llvm/test/CodeGen/ARM/vldm-liveness.mir
    M llvm/test/CodeGen/ARM/vldmia-sched.mir
    M llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir
    M llvm/test/CodeGen/Hexagon/addrmode-immop.mir
    M llvm/test/CodeGen/Hexagon/addrmode-no-rdef.mir
    M llvm/test/CodeGen/Hexagon/bank-conflict-load.mir
    M llvm/test/CodeGen/Hexagon/bank-conflict.mir
    M llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir
    M llvm/test/CodeGen/Hexagon/cext-opt-stack-no-rr.mir
    M llvm/test/CodeGen/Hexagon/cext-unnamed-global.mir
    M llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir
    M llvm/test/CodeGen/Hexagon/early-if-predicator.mir
    M llvm/test/CodeGen/Hexagon/hwloop-dbg-register.mir
    M llvm/test/CodeGen/Hexagon/ifcvt-diamond-ret.mir
    M llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
    M llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir
    M llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/brindirect.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fabs_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/floating_point_vec_arithmetic_operations.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned_r6.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned_r6.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/brindirect.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec_builtin.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations_builtin.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec_builtin.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_4_unaligned.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec_builtin.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_4_unaligned.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec_builtin.mir
    M llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
    M llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir
    M llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
    M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
    M llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
    M llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
    M llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir
    M llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir
    M llvm/test/CodeGen/Mips/micromips-eva.mir
    M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir
    M llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir
    M llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
    M llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
    M llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
    M llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
    M llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
    M llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir
    M llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir
    M llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir
    M llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
    M llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
    M llvm/test/CodeGen/PowerPC/block-placement-1.mir
    M llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir
    M llvm/test/CodeGen/PowerPC/livevars-crash1.mir
    M llvm/test/CodeGen/PowerPC/livevars-crash2.mir
    M llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
    M llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
    M llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir
    M llvm/test/CodeGen/PowerPC/phi-eliminate.mir
    M llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir
    M llvm/test/CodeGen/PowerPC/remove-redundant-li-skip-imp-kill.mir
    M llvm/test/CodeGen/PowerPC/schedule-addi-load.mir
    M llvm/test/CodeGen/PowerPC/sext_elimination.mir
    M llvm/test/CodeGen/PowerPC/shrink-wrap.mir
    M llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir
    M llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir
    M llvm/test/CodeGen/PowerPC/two-address-crash.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/cmplx_cong.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revertcallearly.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-retaining.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wls-search-killed.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wls-search-pred.mir
    M llvm/test/CodeGen/Thumb2/bti-const-island.mir
    M llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir
    M llvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir
    M llvm/test/CodeGen/Thumb2/high-reg-spill.mir
    M llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir
    M llvm/test/CodeGen/Thumb2/m4-sched-ldr.mir
    M llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir
    M llvm/test/CodeGen/Thumb2/mve-tp-loop.mir
    M llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir
    M llvm/test/CodeGen/Thumb2/mve-wls-block-placement.mir
    M llvm/test/CodeGen/Thumb2/phi_prevent_copy.mir
    M llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir
    M llvm/test/CodeGen/Thumb2/postinc-distribute.mir
    M llvm/test/CodeGen/Thumb2/store-prepostinc.mir
    M llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir
    M llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir
    M llvm/test/CodeGen/Thumb2/swp-fixedii.mir
    M llvm/test/CodeGen/Thumb2/swp-regpressure.mir
    M llvm/test/CodeGen/Thumb2/tbb-removeadd.mir
    M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.mir
    M llvm/test/CodeGen/WebAssembly/exception.mir
    M llvm/test/CodeGen/WebAssembly/function-info.mir
    M llvm/test/CodeGen/X86/AMX/amx-fastconfig.mir
    M llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir
    M llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir
    M llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
    M llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
    M llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-constant.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-ptr-add.mir
    M llvm/test/CodeGen/X86/GlobalISel/x32-select-frameIndex.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86-select-frameIndex.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-inttoptr.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-ptrtoint.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-select-frameIndex.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir
    M llvm/test/CodeGen/X86/StackColoring-dbg-invariance.mir
    M llvm/test/CodeGen/X86/adx-commute.mir
    M llvm/test/CodeGen/X86/basic-block-sections-mir-parse.mir
    M llvm/test/CodeGen/X86/block-placement.mir
    M llvm/test/CodeGen/X86/callbr-asm-kill.mir
    M llvm/test/CodeGen/X86/cf-opt-memops.mir
    M llvm/test/CodeGen/X86/codegen-prepare-replacephi.mir
    M llvm/test/CodeGen/X86/codegen-prepare-replacephi2.mir
    M llvm/test/CodeGen/X86/copy-eflags-liveinlists.mir
    M llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir
    M llvm/test/CodeGen/X86/domain-reassignment.mir
    M llvm/test/CodeGen/X86/expand-call-rvmarker.mir
    M llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir
    M llvm/test/CodeGen/X86/fixup-bw-inst.mir
    M llvm/test/CodeGen/X86/heap-alloc-markers.mir
    M llvm/test/CodeGen/X86/implicit-null-checks.mir
    M llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir
    M llvm/test/CodeGen/X86/late-remat-update.mir
    M llvm/test/CodeGen/X86/lea-opt-with-debug.mir
    M llvm/test/CodeGen/X86/limit-split-cost.mir
    M llvm/test/CodeGen/X86/machine-cp-mask-reg.mir
    M llvm/test/CodeGen/X86/movtopush.mir
    M llvm/test/CodeGen/X86/peephole-fold-testrr.mir
    M llvm/test/CodeGen/X86/peephole-recurrence.mir
    M llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir
    M llvm/test/CodeGen/X86/pr38952.mir
    M llvm/test/CodeGen/X86/pr51903.mir
    M llvm/test/CodeGen/X86/pre-coalesce.mir
    M llvm/test/CodeGen/X86/regalloc-copy-hints.mir
    M llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir
    M llvm/test/CodeGen/X86/stack-folding-bmi2.mir
    M llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir
    M llvm/test/CodeGen/X86/statepoint-fixup-call.mir
    M llvm/test/CodeGen/X86/statepoint-fixup-copy-prop-neg.mir
    M llvm/test/CodeGen/X86/statepoint-fixup-copy-prop.mir
    M llvm/test/CodeGen/X86/statepoint-fixup-invoke.mir
    M llvm/test/CodeGen/X86/statepoint-fixup-shared-ehpad.mir
    M llvm/test/CodeGen/X86/statepoint-fixup-undef-def.mir
    M llvm/test/CodeGen/X86/statepoint-fixup-undef.mir
    M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
    M llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
    M llvm/test/CodeGen/X86/statepoint-vreg-folding.mir
    M llvm/test/CodeGen/X86/statepoint-vreg-twoaddr.mir
    M llvm/test/CodeGen/X86/statepoint-vreg.mir
    M llvm/test/CodeGen/X86/tail-call-conditional.mir
    M llvm/test/CodeGen/X86/taildup-callsiteinfo.mir
    M llvm/test/CodeGen/X86/unfoldMemoryOperand.mir
    M llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir
    M llvm/test/CodeGen/X86/x87-reg-usage.mir

  Log Message:
  -----------
  [CodeGen] Convert some tests to opaque pointers (NFC)

These are mostly MIR tests, which I did not handle during previous
conversions.

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