[all-commits] [llvm/llvm-project] 002005: [RISCV] Add integer scalar instructions to isAssoc...

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 002005e6740e6de8f748ed234db08625cc533195
      https://github.com/llvm/llvm-project/commit/002005e6740e6de8f748ed234db08625cc533195
  Author: Hsiangkai Wang <hsiangkai at google.com>
  Date:   2022-12-29 (Thu, 29 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
    M llvm/test/CodeGen/RISCV/addcarry.ll
    M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
    M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
    M llvm/test/CodeGen/RISCV/compress.ll
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/div-by-constant.ll
    M llvm/test/CodeGen/RISCV/div-pow2.ll
    M llvm/test/CodeGen/RISCV/div.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/iabs.ll
    M llvm/test/CodeGen/RISCV/machine-combiner.ll
    M llvm/test/CodeGen/RISCV/mul.ll
    M llvm/test/CodeGen/RISCV/neg-abs.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/sadd_sat.ll
    M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/select-binop-identity.ll
    M llvm/test/CodeGen/RISCV/shadowcallstack.ll
    M llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
    M llvm/test/CodeGen/RISCV/srem-lkk.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/ssub_sat.ll
    M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/uadd_sat.ll
    M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
    M llvm/test/CodeGen/RISCV/urem-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/usub_sat.ll
    M llvm/test/CodeGen/RISCV/usub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/vararg.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll

  Log Message:
  -----------
  [RISCV] Add integer scalar instructions to isAssociativeAndCommutative

Inspired by D138107.

We can add ADD, AND, OR, XOR, MUL, MIN[U]/MAX[U] to isAssociativeAndCommutative
to increase instruction-level parallelism by the existing MachineCombiner pass.

Differential Revision: https://reviews.llvm.org/D140530


  Commit: af5dd2706c845b8bea6ba9fd3e68c1ee982b01fa
      https://github.com/llvm/llvm-project/commit/af5dd2706c845b8bea6ba9fd3e68c1ee982b01fa
  Author: Hsiangkai Wang <hsiangkai at google.com>
  Date:   2022-12-29 (Thu, 29 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/machine-combiner.ll

  Log Message:
  -----------
  [RISCV] Add fmin/fmax scalar instructions to isAssociativeAndCommutative

Follow-up patch of D140530.

We can add FMIN, FMAX to isAssociativeAndCommutative to
increase instruction-level parallelism by the existing MachineCombiner
pass.

Differential Revision: https://reviews.llvm.org/D140602


Compare: https://github.com/llvm/llvm-project/compare/947d529e4194...af5dd2706c84