[all-commits] [llvm/llvm-project] 79d6e9: [RISCV] Prefer ADDI over ORI if the known bits are...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 79d6e9c7130c1b55da188413e9f59e8605fe0902
      https://github.com/llvm/llvm-project/commit/79d6e9c7130c1b55da188413e9f59e8605fe0902
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-28 (Wed, 28 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/test/CodeGen/RISCV/or-is-add.ll
    M llvm/test/CodeGen/RISCV/rv64zba.ll
    M llvm/test/CodeGen/RISCV/vararg.ll

  Log Message:
  -----------
  [RISCV] Prefer ADDI over ORI if the known bits are disjoint.

There is no compressed form of ORI but there is a compressed form
for ADDI.

This also works for XORI since DAGCombine will turn Xor with disjoint
bits in Or.

Note: The compressed forms require a simm6 immediate, but I'm doing
this for the full simm12 range.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D140674