[all-commits] [llvm/llvm-project] 6357b6: [RISCV] Add RISCV::XORI to RISCVDAGToDAGISel::hasA...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6357b6373525f2c6154500727cc55bda2ee6910f
      https://github.com/llvm/llvm-project/commit/6357b6373525f2c6154500727cc55bda2ee6910f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-28 (Wed, 28 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/select-constant-xor.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll

  Log Message:
  -----------
  [RISCV] Add RISCV::XORI to RISCVDAGToDAGISel::hasAllNBitUsers.


  Commit: 9b59207a985026c989cd6afb7c34e3926436ddb1
      https://github.com/llvm/llvm-project/commit/9b59207a985026c989cd6afb7c34e3926436ddb1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-28 (Wed, 28 Dec 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll

  Log Message:
  -----------
  [RISCV] Fix mistakes in fixed-vectors-vreductions-mask.ll command lines. NFC

There were 4 RUN lines, but only 2 of them were unique. I believe
we were trying to test LMUL=1 and LMUL=8 with riscv32 and riscv64.
But put riscv32 on both LMUL=1 lines and riscv64 on both LMUL=8 lines.


Compare: https://github.com/llvm/llvm-project/compare/14b42f21a25c...9b59207a9850