[all-commits] [llvm/llvm-project] cdf09c: [RISCV] Support SRLI in hasAllNBitUsers.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cdf09ce7e774524765b832d714a7fca77b154b44
      https://github.com/llvm/llvm-project/commit/cdf09ce7e774524765b832d714a7fca77b154b44
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-28 (Wed, 28 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll

  Log Message:
  -----------
  [RISCV] Support SRLI in hasAllNBitUsers.

We can recursively look through SRLI if the shift amount is less
than the demanded bits. We can reduce the demanded bit count by
the shift amount and check the users of the SRLI.