[all-commits] [llvm/llvm-project] 46458a: [NFC][AArch64] Add a few vector shuffle tests that...

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 46458aadd427aae2254a6f219e6180252d677e45
      https://github.com/llvm/llvm-project/commit/46458aadd427aae2254a6f219e6180252d677e45
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2022-12-26 (Mon, 26 Dec 2022)

  Changed paths:
    M llvm/test/CodeGen/AArch64/aarch64-vuzp.ll

  Log Message:
  -----------
  [NFC][AArch64] Add a few vector shuffle tests that should be `zip1`

At least, they are equivalent to the `@vzipNoBlend`, which is lowered into zip1.


  Commit: 62fc5f16405a7d39e62044bc461752f3f31bdca0
      https://github.com/llvm/llvm-project/commit/62fc5f16405a7d39e62044bc461752f3f31bdca0
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2022-12-26 (Mon, 26 Dec 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/aarch64-vuzp.ll

  Log Message:
  -----------
  [DAGCombiner] Add a most basic `combineShuffleToZeroExtendVectorInReg()`

Sometimes we end up with a shuffles in DAG that would be
better represented as a `ISD::ZERO_EXTEND_VECTOR_INREG`,
and a failure to do so causes suboptimal codegen in a number of cases,
especially when we will then cast vector to scalar.

I acknowledge, the test changes here are rather underwhelming,
but as with all of codegen, it's always a yak shawing,
and this is the most stripped down version of the patch
that shows *some* effect without having insurmountable amount
of fallout to deal with. The next change resolves this regression.

The transformation will be extended in follow-ups.


  Commit: 83288f8063377f03cbcf3e89c940d2a62c855a96
      https://github.com/llvm/llvm-project/commit/83288f8063377f03cbcf3e89c940d2a62c855a96
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2022-12-26 (Mon, 26 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/test/CodeGen/AArch64/aarch64-vuzp.ll

  Log Message:
  -----------
  [AArch64] Custom lower `ISD::ZERO_EXTEND_VECTOR_INREG`

The baseline legalization for `ISD::ZERO_EXTEND_VECTOR_INREG`
(`VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG`),
blends-in the zeros, but as mentioned e.g.
in b4bd0a404fe26071dab0854dfd9767974909c7c4,
there is no such thing for AArch64.

So some of the shuffles that would be nicely lowered
by `LowerVECTOR_SHUFFLE()`, e.g. into `ZIP1`,
would now be unrecognizable after round-tripping
through `ISD::ZERO_EXTEND_VECTOR_INREG` recognition & legalization.

The most obvious solution is to just custom-lower
`ISD::ZERO_EXTEND_VECTOR_INREG` as the `ZIP1`-with-zeros,
like it would have been originally in that test case.


  Commit: e26e7ed69ac6bb3fdc36c2c01907092ff70c5ff0
      https://github.com/llvm/llvm-project/commit/e26e7ed69ac6bb3fdc36c2c01907092ff70c5ff0
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2022-12-26 (Mon, 26 Dec 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/aarch64-vuzp.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll

  Log Message:
  -----------
  [DAG] `combineShuffleToZeroExtendVectorInReg()`: try to match w/ commuted operands

We don't have any reason to expect that the operand we will match
is on any particular hand of the shuffle, so we should try both.


Compare: https://github.com/llvm/llvm-project/compare/bb778cf36da6...e26e7ed69ac6