[all-commits] [llvm/llvm-project] 3a894f: [AArch64] Lower READCYCLECOUNTER using MRS CNTVCT_EL0

[Salvatore Dipietro via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3a894fd90b0569b4ddd9782e3ab3a4b1e85c0075
      https://github.com/llvm/llvm-project/commit/3a894fd90b0569b4ddd9782e3ab3a4b1e85c0075
  Author: Salvatore Dipietro <dipiets at amazon.com>
  Date:   2022-12-09 (Fri, 09 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/mattr-all.ll
    M llvm/test/CodeGen/AArch64/readcyclecounter.ll

  Log Message:
  -----------
  [AArch64] Lower READCYCLECOUNTER using MRS CNTVCT_EL0

As suggested in D12425 it would be better for the readcyclecounter
function on ARM architecture to use the CNTVCT_EL0 register
(Counter-timer Virtual Count register) instead of the PMCCNTR_EL0
(Performance Monitors Cycle Count Register) because the PMCCNTR_EL0 is a
PMU register which, depending on the configuration, it might always
return zeroes and it doesn't guaranteed to always be increased.

Differential Revision: https://reviews.llvm.org/D136999