[all-commits] [llvm/llvm-project] f9e039: [AArch64] Select SMULL for zero extended vectors w...

[Zain Jaffal via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f9e0390751cb5eefbbbc191f851c52422acacab1
      https://github.com/llvm/llvm-project/commit/f9e0390751cb5eefbbbc191f851c52422acacab1
  Author: Zain Jaffal <z_jaffal at apple.com>
  Date:   2022-12-08 (Thu, 08 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/aarch64-smull.ll

  Log Message:
  -----------
  [AArch64] Select SMULL for zero extended vectors when top bit is zero

we can safely replace a `zext` instruction with `sext` if the top bit is zero. This is useful because we can select `smull` when both operands are sign extended.

Reviewed By: fhahn, dmgreen

Differential Revision: https://reviews.llvm.org/D134711