[all-commits] [llvm/llvm-project] 66ff07: [RISCV] Support F16 vectors with Zfhmin+Zvfh.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 66ff0731822a7f1ffdc131af7344c19a605a9ec2
      https://github.com/llvm/llvm-project/commit/66ff0731822a7f1ffdc131af7344c19a605a9ec2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-07 (Wed, 07 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd.ll

  Log Message:
  -----------
  [RISCV] Support F16 vectors with Zfhmin+Zvfh.

I've enabled Zfhmin on 2 basic tests to show this isn't
completely broken.

Reviewed By: monkchiang

Differential Revision: https://reviews.llvm.org/D139562