[all-commits] [llvm/llvm-project] 372240: [TableGen] More named sub-operands work.

[James Y Knight via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 372240dfe3d5a933d9585663e15c4b6173ff23c8
      https://github.com/llvm/llvm-project/commit/372240dfe3d5a933d9585663e15c4b6173ff23c8
  Author: James Y Knight <jyknight at google.com>
  Date:   2022-12-07 (Wed, 07 Dec 2022)

  Changed paths:
    M llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp
    M llvm/lib/Target/ARC/ARCInstrFormats.td
    M llvm/lib/Target/ARC/ARCInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrFormats.td
    M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    M llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
    M llvm/lib/Target/Mips/Mips16InstrInfo.td
    M llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
    M llvm/lib/Target/Sparc/SparcInstrInfo.td
    A llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td
    M llvm/test/TableGen/RegisterEncoder.td
    M llvm/utils/TableGen/CodeEmitterGen.cpp
    M llvm/utils/TableGen/CodeGenInstruction.cpp
    M llvm/utils/TableGen/CodeGenInstruction.h
    M llvm/utils/TableGen/DecoderEmitter.cpp
    M llvm/utils/TableGen/VarLenCodeEmitterGen.cpp

  Log Message:
  -----------
  [TableGen] More named sub-operands work.

Commit a538d1f13a13 first added support for named sub-operands in
CodeEmitterGen. We now add a few more features to that, enabling
further target cleanups.

1. Adds support for handling an EncoderMethod in a sub-operand in
CodeEmitterGen. Previously, the specified encoder of a sub-operand was
ignored, and only the default used.

2. Adds support for sub-operands in DecoderEmitter, along with support
for tied sub-operands.

The changes to the decoder required a few minor tweaks to a few
targets, where existing brokeness was exposed. In order to keep this
patch small, I left FIXMEs which will be addressed in upcoming
patches. (Except MIPS16, since its object file emission/decoding is
totally broken).

Differential Revision: https://reviews.llvm.org/D137653


  Commit: 099001979fe82a069d5572dffea472b339878c75
      https://github.com/llvm/llvm-project/commit/099001979fe82a069d5572dffea472b339878c75
  Author: James Y Knight <jyknight at google.com>
  Date:   2022-12-07 (Wed, 07 Dec 2022)

  Changed paths:
    M llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
    M llvm/lib/Target/Sparc/SparcInstr64Bit.td
    M llvm/lib/Target/Sparc/SparcInstrInfo.td
    A llvm/test/MC/Disassembler/Sparc/sparc-coproc.txt
    M llvm/test/MC/Disassembler/Sparc/sparc-mem.txt
    M llvm/test/MC/Disassembler/Sparc/sparc-special-registers.txt
    M llvm/test/MC/Disassembler/Sparc/sparc-v9.txt
    M llvm/test/MC/Disassembler/Sparc/sparc.txt

  Log Message:
  -----------
  [SPARC] Simplify instruction decoder.

After https://reviews.llvm.org/D137653 named sub-operands can be used
in the auto-generated instruction decoders. This allows the
auto-generated decoders to work properly, so all the hand-coded
decoders in the sparc target can be removed.

In some instances, a manually-written decoder had not been implemented
for an instruction, and thus that instruction was not decoded
properly. These have been fixed (and tests added).

Differential Revision: https://reviews.llvm.org/D137727


Compare: https://github.com/llvm/llvm-project/compare/b12fe0d429aa...099001979fe8