[all-commits] [llvm/llvm-project] 72d76a: [mlir][bufferize] lower allocation alignment from ...

[Emilio Cota via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 72d76a2403459a38a1d6daae62de6945097db8f9
      https://github.com/llvm/llvm-project/commit/72d76a2403459a38a1d6daae62de6945097db8f9
  Author: Emilio Cota <ecg at google.com>
  Date:   2022-12-07 (Wed, 07 Dec 2022)

  Changed paths:
    M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
    M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir
    M mlir/test/Dialect/Linalg/one-shot-bufferize.mlir
    M mlir/test/Dialect/Tensor/bufferize.mlir
    M mlir/test/Dialect/Tensor/one-shot-bufferize.mlir

  Log Message:
  -----------
  [mlir][bufferize] lower allocation alignment from 128 to 64 bytes

While it is unlikely to matter in practice, there is no reason
for this value to be larger than it should be. 64 bytes is the
size of a cache line in most machines, and we can fit a full
512-bit vector in it.

Reviewed By: springerm
Differential Revision: https://reviews.llvm.org/D139434