[all-commits] [llvm/llvm-project] 7b50c1: [RISCV] Codegen support for Zfhmin.

[Monk Chiang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7b50c183601adf8cacf20f3644cb0f72c7cd1125
      https://github.com/llvm/llvm-project/commit/7b50c183601adf8cacf20f3644cb0f72c7cd1125
  Author: Monk Chiang <monk.chiang at sifive.com>
  Date:   2022-12-06 (Tue, 06 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/CodeGen/RISCV/calling-conv-half.ll
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/half-arith-strict.ll
    M llvm/test/CodeGen/RISCV/half-arith.ll
    M llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/half-br-fcmp.ll
    M llvm/test/CodeGen/RISCV/half-convert-strict.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
    M llvm/test/CodeGen/RISCV/half-fcmp.ll
    M llvm/test/CodeGen/RISCV/half-frem.ll
    M llvm/test/CodeGen/RISCV/half-imm.ll
    M llvm/test/CodeGen/RISCV/half-intrinsics.ll
    M llvm/test/CodeGen/RISCV/half-isnan.ll
    M llvm/test/CodeGen/RISCV/half-mem.ll
    M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/half-round-conv.ll
    M llvm/test/CodeGen/RISCV/half-select-fcmp.ll
    M llvm/test/CodeGen/RISCV/half-select-icmp.ll
    A llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll
    A llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll
    A llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll
    A llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
    A llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll
    A llvm/test/CodeGen/RISCV/zfhmin-imm.ll

  Log Message:
  -----------
  [RISCV] Codegen support for Zfhmin.

The Zfhmin subset only has FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S.
If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included.
Since most instructions are not included for Zfhmin, so most operations are promoted.
The patch primarily about making f16 a legal type.

RISC-V ISA info:
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139391