[all-commits] [llvm/llvm-project] 70de0e: [VP][RISCV] Add vp.fshl/fshr and RISC-V support.

[Yeting Kuo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 70de0e014013b4d97febe6704881a9a8c893d078
      https://github.com/llvm/llvm-project/commit/70de0e014013b4d97febe6704881a9a8c893d078
  Author: Yeting Kuo <yeting.kuo at sifive.com>
  Date:   2022-12-07 (Wed, 07 Dec 2022)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/include/llvm/IR/VPIntrinsics.def
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
    A llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
    M llvm/unittests/IR/VPIntrinsicTest.cpp

  Log Message:
  -----------
  [VP][RISCV] Add vp.fshl/fshr and RISC-V support.

The patch made VectorLegalizer expand ISD::VP_FSHL and ISD::VP_FSHR to
achieve the codegen.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D138379