[all-commits] [llvm/llvm-project] 8d30b9: [RISCV] Move VSPILL/VRELOAD expansion for vector t...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8d30b9e64f7e4140c5eba9099b9a26ac7f806233
      https://github.com/llvm/llvm-project/commit/8d30b9e64f7e4140c5eba9099b9a26ac7f806233
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-12-06 (Tue, 06 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    R llvm/test/CodeGen/RISCV/rvv/undef-subreg-range.mir
    M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

  Log Message:
  -----------
  [RISCV] Move VSPILL/VRELOAD expansion for vector tuples to eliminateFrameIndex.

We need a scratch GPR to increment the base pointer for each subsequent
register. We currently reuse the input GPR for the base pointer without
declaring it as a Def of the pseudo.

We can't add it as a Def of the pseudo at creation time because it doesn't
get register allocated. This was tried in D109405.

Seems the only choice we have is to scavenge the GPR. This patch
moves the expansion to eliminateFrameIndex where we can create
virtual registers that will be scavenged. This also eliminates the
extra operand for passing vlenb from frame lowering to expand pseudos.

I need to do more testing on real world code, but wanted to get this
up for early review.

I hope this will fix the issue reported in D123394, but I haven't
checked yet.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D139169