[all-commits] [llvm/llvm-project] 94e7e5: [AArch64] implement GPR (U/S)(MIN/MAX) instruction...

[Ties Stuij via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 94e7e58fa4d32b0e0bfad395b2cc219c9dccd5b2
      https://github.com/llvm/llvm-project/commit/94e7e58fa4d32b0e0bfad395b2cc219c9dccd5b2
  Author: Ties Stuij <ties.stuij at arm.com>
  Date:   2022-12-06 (Tue, 06 Dec 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/min-max.ll

  Log Message:
  -----------
  [AArch64] implement GPR (U/S)(MIN/MAX) instruction SDag support

Using SelectionDag, lower umin, umax, smin, smax intrinsics to corresponding
UMIN, UMAX, SMIN, SMAX instructions when feat CSSC is available.

See specs for corresponding immediate and register versions in:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D138813