[all-commits] [llvm/llvm-project] 132dc4: [RISCV] Generate .cfi_def_cfa_expression for RVV s...

[Sergey Kachkov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 132dc442ba3c137c9b3595a76a3214c96c59d884
      https://github.com/llvm/llvm-project/commit/132dc442ba3c137c9b3595a76a3214c96c59d884
  Author: Sergey Kachkov <sergey.kachkov at syntacore.com>
  Date:   2022-12-06 (Tue, 06 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
    M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
    M llvm/test/CodeGen/RISCV/rvv/localvar.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

  Log Message:
  -----------
  [RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment

Cannonical frame address after RVV stack adjustment is sp + StackSize +
RVVStackSize * vlenb, and since vlenb is unknown at compile-time (but it
is a constant for particular HW implementation), emit
.cfi_def_cfa_expression so libunwind can read VLENB CSR register at
run-time and obtain correct frame address.

Fixes https://github.com/llvm/llvm-project/issues/58356 (but additional
run-time support for reading CSR may be required)

Differential Revision: https://reviews.llvm.org/D136263