[all-commits] [llvm/llvm-project] 0d03ba: [mlir][tensor] Implement TilingInterface for tenso...

[Han-Chung Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0d03ba62c55f5fc1edf28ccffe9dd4ffa3edd4d0
      https://github.com/llvm/llvm-project/commit/0d03ba62c55f5fc1edf28ccffe9dd4ffa3edd4d0
  Author: Hanhan Wang <hanchung at google.com>
  Date:   2022-12-05 (Mon, 05 Dec 2022)

  Changed paths:
    M mlir/include/mlir/Dialect/Affine/Utils.h
    M mlir/lib/Dialect/Tensor/IR/CMakeLists.txt
    M mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp
    A mlir/test/Dialect/Tensor/tiling.mlir
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  [mlir][tensor] Implement TilingInterface for tensor.pack op.

We can compute the offsets and sizes for the slice of input because the
iteration domain is defined over outer loops. If the dimension is tiled,
the i-th index is the product of offset_i and inner_tile_i.

Different from tiling a pad op, we do not have to deal with reading zero
data from input. Because the tiling sizes are indicated to packed outer
dimensions. We will read either the entire tile or partial tile for each
packed tile. The scf.if and tensor.generate ops are not needed in this
context.

Co-authored-by: Lorenzo Chelini <l.chelini at icloud.com>

Reviewed By: rengolin, mravishankar

Differential Revision: https://reviews.llvm.org/D138631