[all-commits] [llvm/llvm-project] 186c19: [SDAG] Allow scalable vectors in SimplifyDemanded ...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 186c1922611501b701128987a5c938287d048cd7
      https://github.com/llvm/llvm-project/commit/186c1922611501b701128987a5c938287d048cd7
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-12-05 (Mon, 05 Dec 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/active_lane_mask.ll
    M llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp

  Log Message:
  -----------
  [SDAG] Allow scalable vectors in SimplifyDemanded routines

This is a continuation of the series of patches adding lane wise support for scalable vectors in various knownbit-esq routines.

The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.

Differential Revision: https://reviews.llvm.org/D137190