[all-commits] [llvm/llvm-project] 5ecd36: Reapply "[CodeGen] Add new pass for late cleanup o...

[Jonas Paulsson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5ecd363295089ad2db3c428ab1ee08ef1864ce3b
      https://github.com/llvm/llvm-project/commit/5ecd363295089ad2db3c428ab1ee08ef1864ce3b
  Author: Jonas Paulsson <paulsson at linux.vnet.ibm.com>
  Date:   2022-12-05 (Mon, 05 Dec 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
    M llvm/include/llvm/CodeGen/MachinePassRegistry.def
    M llvm/include/llvm/CodeGen/Passes.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/lib/CodeGen/CMakeLists.txt
    M llvm/lib/CodeGen/CodeGen.cpp
    A llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
    M llvm/lib/CodeGen/TargetPassConfig.cpp
    M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
    M llvm/test/CodeGen/AArch64/O3-pipeline.ll
    M llvm/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll
    M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
    M llvm/test/CodeGen/AMDGPU/cc-update.ll
    M llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/multilevel-break.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
    M llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll
    M llvm/test/CodeGen/AMDGPU/si-unify-exit-return-unreachable.ll
    M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/ARM/O3-pipeline.ll
    M llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll
    M llvm/test/CodeGen/ARM/fpclamptosat.ll
    M llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
    M llvm/test/CodeGen/ARM/jump-table-islands.ll
    M llvm/test/CodeGen/ARM/reg_sequence.ll
    M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
    M llvm/test/CodeGen/M68k/pipeline.ll
    M llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
    M llvm/test/CodeGen/Mips/llvm-ir/shl.ll
    M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
    M llvm/test/CodeGen/PowerPC/cgp-select.ll
    M llvm/test/CodeGen/PowerPC/fast-isel-branch.ll
    M llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
    M llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
    A llvm/test/CodeGen/SystemZ/frame-28.mir
    M llvm/test/CodeGen/Thumb/frame-access.ll
    M llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
    M llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll
    M llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
    M llvm/test/CodeGen/X86/AMX/amx-across-func.ll
    M llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
    M llvm/test/CodeGen/X86/fast-isel-stackcheck.ll
    M llvm/test/CodeGen/X86/fshl.ll
    M llvm/test/CodeGen/X86/masked_load.ll
    M llvm/test/CodeGen/X86/oddshuffles.ll
    M llvm/test/CodeGen/X86/opt-pipeline.ll
    M llvm/test/CodeGen/X86/sdiv_fix_sat.ll
    M llvm/test/CodeGen/X86/shift-i128.ll
    M llvm/test/CodeGen/X86/ushl_sat_vec.ll
    M llvm/test/CodeGen/X86/vec_extract.ll
    M llvm/test/CodeGen/X86/vec_shift5.ll
    M llvm/test/CodeGen/XCore/scavenging.ll

  Log Message:
  -----------
  Reapply "[CodeGen] Add new pass for late cleanup of redundant definitions."

This reverts commit 122efef8ee9be57055d204d52c38700fe933c033.

- Patch fixed to not reuse definitions from predecessors in EH landing pads.
- Late review suggestions (by MaskRay) have been addressed.
- M68k/pipeline.ll test updated.
- Init captures added in processBlock() to avoid capturing structured bindings.
- RISCV has this disabled for now.

Original commit message:

A new pass MachineLateInstrsCleanup is added to be run after PEI.

This is a simple pass that removes redundant and identical instructions
whenever found by scanning the MF once while keeping track of register
definitions in a map. These instructions are typically immediate loads
resulting from rematerialization, and address loads emitted by target in
eliminateFrameInde().

This is enabled by default, but a target could easily disable it by means of
'disablePass(&MachineLateInstrsCleanupID);'.

This late cleanup is naturally not "optimal" in removing instructions as it
is done by looking at phys-regs, but still quite effective. It would be
desirable to improve other parts of CodeGen and avoid these redundant
instructions in the first place, but there are no ideas for this yet.

Differential Revision: https://reviews.llvm.org/D123394

Reviewed By: RKSimon, foad, craig.topper, arsenm, asb