[all-commits] [llvm/llvm-project] 7969ab: [SDAG] Allow scalable vectors in ComputeKnownBits ...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7969ab85e0a413eeba2bf4360f0c7ea6c5f00e4c
      https://github.com/llvm/llvm-project/commit/7969ab85e0a413eeba2bf4360f0c7ea6c5f00e4c
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-12-05 (Mon, 05 Dec 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
    M llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll

  Log Message:
  -----------
  [SDAG] Allow scalable vectors in ComputeKnownBits (try 2)

This was previously reverted due to a hang on a Hexagon bot.  This turned out to be a bug in the Hexagon backend around how splat_vectors are legalized (which they're using for fixed length vectors!).  I adjusted this patch to remove the implicit truncate support.  This hides the hexagon bug for now, and unblocks the rest of the change.

Original commit message:

This is the SelectionDAG equivalent of D136470, and is thus an alternate patch to D128159.

The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.

This patch also includes an implementation for SPLAT_VECTOR as without it, the lane wise reasoning has no base case. The original patch which inspired this (D128159), also included STEP_VECTOR. I plan to do that as a separate patch.

Differential Revision: https://reviews.llvm.org/D137140