[all-commits] [llvm/llvm-project] b77533: [RISCV] Fold low 12 bits into instruction during f...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b77533306876fc807e58e355d95d848a0077131f
      https://github.com/llvm/llvm-project/commit/b77533306876fc807e58e355d95d848a0077131f
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-12-02 (Fri, 02 Dec 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/test/CodeGen/RISCV/branch-relaxation.ll
    M llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
    M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
    M llvm/test/CodeGen/RISCV/pr58286.ll
    M llvm/test/CodeGen/RISCV/vararg.ll

  Log Message:
  -----------
  [RISCV] Fold low 12 bits into instruction during frame index elimination

Fold the low 12 bits of an immediate offset into the offset field of the using instruction. That using instruction will be a load, store, or addi which performs an add of a signed 12-bit immediate as part of it's operation. Splitting out the low bits allows the high bits to be generated via a single LUI instead of needing an LUI/ADDI pair.

The codegen effect of this is mostly converting cases where "split addi" kicks in to using LUI + a folded offset. There are a couple of straight dynamic instruction count wins, and using a canonical LUI is probably better than a chain of SP adds if the dynamic instruction count is equal.

Differential Revision: https://reviews.llvm.org/D139037